1. Field of the Invention
The present invention relates to a data processing apparatus and method for performing conversion from a fixed point number to a floating point number, and in particular to techniques for the handling of rounding when performing such conversion.
2. Description of the Prior Art
A floating point number can be expressed as follows:
            ±      1.        ⁢    x    *          2      y                                                where            ⁢                          :                        ⁢            x                    =          fraction                                                          1.            ⁢            x                    =                      significand            ⁢                                                  ⁢                          (                              also                ⁢                                                                  ⁢                known                ⁢                                                                  ⁢                as                ⁢                                                                  ⁢                the                ⁢                                                                  ⁢                mantissa                            )                                                                    y          =          exponent                    
A fixed point number format is one where the numbers are expressed by a predetermined number of bits, with the decimal point being considered to exist at a predetermined location within the number of bits. An integer is hence an example of a fixed point number in which the decimal point is considered to exist immediately to the right of the least significant bit position.
If the fixed point number consists of m bits, and is converted to a floating point number having an n-bit significand, it is often the case that n is less than m, and in such situations the floating point number needs to be subjected to a rounding process, as a result of which it may or may not be necessary to add a rounding increment to the significand in order to produce the correct n-bit significand for the rounded floating point number.
Whether a rounding increment will or will not be required will depend on the bit location of the most significant bit of the value expressed within the m-bit fixed point number. For an unsigned number or a positive signed number, this bit location will be given by the most significant logic one value in the number, whereas for a negative signed number, this bit location will be given by the most significant logic zero value in the number. If this bit location is within the least significant n bits of the m-bit fixed point number, then no rounding increment will need to be introduced, since the value can directly be expressed within the n-bit significand of the floating point number. However, if the most significant bit is at a location greater than the least significant n bits of the m-bit fixed point number, then it may be necessary to introduce a rounding increment dependent on the value of a certain number of least significant bits of the m-bit fixed point number.
Traditionally, when converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, the following sequence of steps is performed to produce the n-bit significand:    1. The fixed point number is evaluated to determine if it is a signed negative number. If so, the number is negated and a logic one value is added to the negated value, thereby producing a two's complement version of the fixed point number.    2. The fixed point number, or the modified version produced in step 1 above in the event of a signed negative number, is then subjected to a leading one determination process in order to determine the location of the most significant bit of the value expressed within the m-bit fixed point number.    3. A left shift operation is then applied based on the leading one determination in order to normalise the number.    4. A rounding determination is then performed. If following the above normalisation process there are now only n bits or less remaining in the number, then no rounding is required since the entire value can be directly represented within the n-bit significand. However, if more than n bits are still remaining, then rounding may be appropriate depending on the value of certain least significant bits of the normalised number.    5. If rounding is required, then a rounding increment is introduced at the least significant bit of the destination precision. Hence, by way of example, if the floating point number is a single precision floating point number, and hence the significand is 24 bits in length, then if the normalised result has 28 bits (bits 0 to 27) a rounding increment if required will be introduced at bit 4, since bit 4 is the least significant bit of the 24-bit significand.
The above process is inherently serial, but it is desirable having regard to performance to try and perform some of the steps in parallel.
It is often the case that logic provided to perform such conversion operations is also used for other operations. For example, the logic provided to perform addition operations may also be re-used for such conversion operations. One particular arrangement of adder logic employs two split data paths, referred to as the far path and the near path. The near path is used for unlike signed additions (USAs) with equal exponents or exponents differing by one and significands guaranteed to differ by less than one. The far path handles all other additions. In the near path, no rounding of the result will be required but normalisation may be required due to massive cancellation. Such normalisation logic is not required in the far path. However, in the far path it is necessary to provide logic to account for rounding due to the fact that the input significands may need more than a 1-bit alignment. Through the use of the near and far paths, the pipeline depth of the pipeline required to perform addition can be reduced, since one path requires normalisation whilst the other does not, and one path requires rounding whilst the other does not.
When performing conversion operations in such adder logic, it is required to pass the conversion operation through the near path, since the near path provides the required normalisation logic. However, the near path would not normally have rounding logic provided, and accordingly there is a problem in performing any required rounding when performing such conversion operations. One way to solve this problem is to add a further final stage to the near path to allow such rounding to be performed, but this clearly adversely affects potential performance benefits that can be achieved by using an adder constructed with a near path and a far path.
The performance problem resulting from the provision of additional logic to perform a final rounding process is not limited to the above far path/near path implementation, but instead it is clear that performance of conversion operations will in general be adversely affected if additional rounding logic needs to be provided after the normalisation step.
Accordingly, it would be desirable to provide an improved technique for performing any required rounding when converting a fixed point number to a floating point number, so as to improve the speed of the operation.